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a ddendum to c505/c505c user 's manual 0 9 .9 7 c 5 0 5 a c 5 0 5 c a 8-bit cmos microcontroller ht tp://www .siemens.de/ semiconductor/
semiconductor group i-2 general information c515c edition 09.97 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 97. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered.
semiconductor group i-1 contents page general information c505a 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 -1 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5 2 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.1 program memory, "code space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2.2 data memory, "data space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2.3 general purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2.4 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 3 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 3.1 a/d converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 3.2 a/d converter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.3 a/d converter clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 3.4 a/d conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8 3.5 a/d converter calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 3.5.1 a/d converter analog input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13 4 otp memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.1 programming configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 4.4 programming mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 4.4.1 basic programming mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 4.4.2 otp memory access mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 4.5 program / read otp memory bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7 4.6 lock bits programming / read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9 4.6.1 access of version bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11 4.7 otp verification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12 5 device specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5- 2 5.3 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 5.4 ac characteristics (12 mhz, 0.5 duty cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7 5.5 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle) . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 5.6 ac characteristics (20 mhz, 0.5 duty cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12 5.7 otp memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17 5.7.1 programming mode timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17 5.7.2 otp verification mode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-21 5.8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 6 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
semiconductor group 1-1 introduction c505a 1 introduction the c505a is an enhanced, upgraded version of the c505-2r eight bit microcontroller and incorporates more on-chip ram, a 10-bit a/d converter and 32k bytes of on-chip otp memory. with a maximum external clock rate of 20 mhz, the c505a has an instruction cycle time of 300 ns. with the c505a-4e fast otp programming cycles are achieved (1 byte in 100 m sec). also several levels of otp memory protection can be selected. the basic functionality of the c505a-4e as a microcontroller is identical to the c505a-l (romless part) functionality. therefore, the programmable c505a-4e typically can be used for prototype system design. the c505a-4e basically operates with internal otp and/or external program memory. the c505a- l is identical to the c505a-4e, except that it lacks the on-chip otp memory. therefore, in this documentation the term c505a refers to all versions within this specification unless otherwise noted. the C505CA-4e and C505CA-l, are identical to the c505a-4e and the c505a-l respectively, except that they have, in addition, the full can interface. the term c505a refers to all the above four versions within this documentation unless otherwise noted. figure 1-1 shows the different functional units of the c505a and figure 1-2 shows the simplified logic symbol of the c505a. figure 1-1 c505a functional units note: this specification describes only the improved functionality over c505/c505c. please refer to the c505/c505c users manual for further details. oscillator watchdog 10-bit adc t0 t1 cpu 8-bit usart i/o i/o 8 digit. i/o i/o otp 32k 8 ram 256 8 xram 1 k 8 on-chip emulation support module timer 2 watchdog timer 8 analog inputs / full-can controller 8 datapointers i/o (2-bit i/o port) port 0 port 1 port 2 port 4 port 3 enhancements over c505/c505c. C505CA only.
introduction c505a semiconductor group 1-2 listed below is a summary of the main features of the c505a family: ? fully compatible to standard 8051 microcontroller ? superset of the 8051 architecture with 8 datapointers ? up to 20 mhz operating frequency C 375 ns instruction cycle time @ 16 mhz C 300 ns instruction cycle time @ 20 mhz (50 % duty cycle) ? 32k byte on-chip otp memory C c505a-4e : programmable otp versions C c505a-l : without on-chip program memory C alternatively up to 64 k bytes of external program memory ? 256 byte on-chip ram ? 1 k byte on-chip xram ? five ports: 32 + 2 digital i/o lines(port 1 with mixed analog/digital i/o capability) ? three 16-bit timers/counters C timer 0 / 1 (c501 compatible) C timer 2 with 4 channels for 16-bit capture/compare operation ? full can module (C505CA only) C 256 register/data bytes located in external data memory area C 1 mbaud can baudrate when operating frequency is equal to or above 8 mhz C internal can clock prescaler when input frequency is over 10 mhz ? full duplex serial interface with programmable baudrate generator (usart) ? 10-bit a/d converter with 8 multiplexed inputs C built-in self calibration ? twelve interrupt sources with four priority levels ? on-chip emulation support logic Cenhanced hooks technology tm 1) ? programmable 15-bit watchdog timer ? oscillator watchdog ? fast power on reset ? power saving modes C slow-down mode C idle mode (can be combined with slow-down mode) C software power-down mode with wake up capability through p3.2/int0 or p4.1/rxdc pin ? p-mqfp-44 package ? pin configuration is compatible to c501, c504, c511/c513-family, c505, c505c ? temperature ranges: sab-c505a versions t a = 0 to 70 c saf-c505a versions t a = C 40 to 85 c sah-c505a versions t a = C 40 to 110 c (max. operating frequency: tbd) sak-c505a versions t a = C40 to 125 c (max. operating frequency: 12 mhz with 50 % duty cycle) 1 enhanced hooks technology is a trademark and patent of metalink corporation licensed to siemens.
semiconductor group 1-3 introduction c505a figure 1-2 logic symbol port 0 8-bit digital i/o port 1 8-bit digital i/o / port 2 8-bit digital i/o port 3 8-bit digital i/o xtal1 xtal2 reset ea ale psen c505a v aref v cc v ss v agnd 8-bit analog inputs rxdc txdc port 4 2-bit digital i/o C505CA only. C505CA
introduction c505a semiconductor group 1-4 1.1 pin configuration this section shows the pin configuration of the c505a in the p-mqfp-44 package. figure 1-3 pin configuration (top view) p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 ea p4.1 / rxdc p2.5 / a13 ale p2.6 / a14 p2.7 / a15 psen p2.4 / a12 p2.3 / a11 p2.2 / a10 p2.1 / a9 p2.0 / a8 v cc xtal1 xtal2 p3.7 / rd p3.6 / wr v ss 33 34 35 36 37 38 39 40 41 42 43 44 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1234567 89 10 11 c505a p0.3 / ad3 p0.2 / ad2 p0.1 / ad1 v aref v agnd p1.1 / an1 / int4 / cc1 p1.2 / an2 / int5 / cc2 p1.3 / an3 / int6 / cc3 p1.4 / an4 p0.0 / ad0 p1.0 / an0 / int3 / cc0 p1.5 / an5 / t2ex p1.6 / an6 / clkout p1.7 / an7 / t2 reset p3.0 / rxd p3.1 / txd p3.2 / int0 p3.3 / int1 p3.4 / t0 p3.5 / t1 p4.0 / txdc C505CA this pin functionality is available in the C505CA only.
semiconductor group 1-5 introduction c505a 1.2 pin definitions and functions this section describes all external signals of the c505a with its function. table 1-1 : pin definitions and functions symbol pin number i/o *) function p1.0-p1.7 40-44,1-3 40 41 42 43 44 1 2 3 i/o port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. port 1 pins can be used for digital input/output or as analog inputs of the a/d converter. port 1 pins that have 1s written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. as inputs, port 1 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. port 1 pins are assigned to be used as analog inputs via the register p1ana. as secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). the secondary functions are assigned to the pins of port 1 as follows: p1.0 / an0 / int3 / cc0 analog input channel 0 interrupt 3 input / capture/compare channel 0 i/o p1.1 / an1 / int4 / cc1 analog input channel 1/ interrupt 4 input / capture/compare channel 1 i/o p1.2 / an2 / int5 / cc2 analog input channel 2 / interrupt 5 input / capture/compare channel 2 i/o p1.3 / an3 / int6 / cc3 analog input channel 3 interrupt 6 input / capture/compare channel 4 i/o p1.4 / an4 analog input channel 4 p1.5 / an5 / t2ex analog input channel 5 / timer 2 external reload / trigger input p1.6 / an6 / clkout analog input channel 6 / system clock output p1.7 / an7 / t2 analog input channel 7 / counter 2 input *) i = input o = output
introduction c505a semiconductor group 1-6 reset 4 i reset a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal diffused resistor to v ss permits power-on reset using only an external capacitor to v cc . p3.0-p3.7 5, 7-13 5 7 8 9 10 11 12 13 i/o port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. port 3 pins that have 1s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. as inputs, port 3 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for txd and wr ). the secondary functions are assigned to the pins of port 3 as follows: p3.0 / rxd receiver data input (asynch.) or data input/output (synch.) of serial interface p3.1 / txd transmitter data output (asynch.) or clock output (synch.) of serial interface p3.2 / int0 external interrupt 0 input / timer 0 gate control input p3.3 / int1 external interrupt 1 input / timer 1 gate control input p3.4 / t0 timer 0 counter input p3.5 / t1 timer 1 counter input p3.6 / wr wr control output; latches the data byte from port 0 into the external data memory p3.7 / rd rd control output; enables the external data memory *) i = input o = output table 1-1 : pin definitions and functions (contd) symbol pin number i/o *) function
semiconductor group 1-7 introduction c505a p4.0 p4.1 6 28 i/o i/o port 4 is a 2-bit quasi-bidirectional port with internal pull-up arrangement. port 4 pins that have 1s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. as inputs, port 4 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. the output latch corresponding to the secondary function rxdc must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the two pins of port 4 as follows (C505CA only) : p4.0 / txdc transmitter output of can controller p4.1 / rxdc receiver input of can controller xtal2 14 o xtal2 output of the inverting oscillator amplifier. xtal1 15 i xtal1 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. to operate above a frequency of 16 mhz, a duty cycle of the etxernal clock signal of 50 % should be maintained. minimum and maximum high and low times as well as rise/ fall times specified in the ac characteristics must be observed. *) i = input o = output table 1-1 : pin definitions and functions (contd) symbol pin number i/o *) function
introduction c505a semiconductor group 1-8 p2.0-p2.7 18-25 i/o port 2 is a an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullup transistors when issuing 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 issues the contents of the p2 special function register and uses only the internal pullup resistors. psen 26 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every three oscillator periods except during external data memory accesses. remains high during internal program execution. this pin should not be driven during reset operation. ale 27 o the address latch enable output is used for latching the low-byte of the address into external memory during normal operation. it is activated every three oscillator periods except during an external data memory access. when instructions are executed from internal otp (ea =1) the ale generation can be disabled by bit eale in sfr syscon. ale should not be driven during reset operation. *) i = input o = output table 1-1 : pin definitions and functions (contd) symbol pin number i/o *) function
semiconductor group 1-9 introduction c505a ea 29 i external access enable when held at high level, instructions are fetched from the internal otp memory when the pc is less than 8000h. when held at low level, the c505a/C505CA fetches all instructions from external program memory. ea should not be driven during reset operation. for the c505a-l and the C505CA-l this pin must be tied low. p0.0-p0.7 37-30 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float, and in that state can be used as high-impendance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. in this application it uses strong internal pullup transistors when issuing 1s. v aref 38 C reference voltage for the a/d converter. v agnd 39 C reference ground for the a/d converter. v ss 16 C ground (0v) v cc 17 C power supply (+5v) *) i = input o = output table 1-1 : pin definitions and functions (contd) symbol pin number i/o *) function
semiconductor group 2-1 memory organization c505a 2 memory organization the c505a cpu manipulates operands in the following four address spaces: C up to 64 kbytes of program memory (32k on-chip otp memory for c505a-4e) C up to 64 kbytes of external data memory C 256 bytes of internal data memory C 1 kbytes of internal xram data memory C 256 bytes can controller registers / data memory (C505CA only) C a 128 byte special function register area figure 2-1 illustrates the memory address spaces of the c505a. figure 2-1 c505a memory map internal xram int. can contr. (256 byte) (1 k byte) not used ffff h 8000 h 7fff h 0000 h "code space" int. (ea = 1) ext. (ea = 0) "internal data space" indirect direct addr. 7f h 00 h internal ram special function regs. 80 h ff h 80 h ff h addr. ext. internal ram "data space" 0000 h fc00 h ffff h f7ff h f700 h f6ff h ext. data memory alternatively ext. data memory internal data space f700 h -f7ff h : device can area unused area internal xram c505a - f700 h -fbff h fc00 h -ffff h C505CA f700 h -f7ff h f800 h -fbff h fc00 h - ffff h see table below for detailed data memory partitioning
memory organization c505a semiconductor group 2-2 2.1 program memory, "code space" the c505a-4e has 32 kbytes of on-chip otp program memory which can be externally expanded up to 64 kbytes. if the ea pin is held high, the c505a-4e executes program code out of the otp memory unless the program counter address exceeds 7fff h . address locations 8000 h through ffff h are then fetched from the external program memory. if the ea pin is held low, the c505a fetches all instructions from the external program memory. 2.2 data memory, "data space" the data memory address space consists of an internal and an external memory space. the internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of ram, the upper 128 bytes of ram, and the 128 byte special function register (sfr) area. while the upper 128 bytes of data memory and the sfr area share the same address locations, they are accessed through different addressing modes. the lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of ram can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. four 8-register banks, each bank consisting of eight 8-bit general-purpose registers, occupy locations 0 through 1f h in the lower ram area. the next 16 bytes, locations 20 h through 2f h , contain 128 directly addressable bit locations. the stack can be located anywhere in the internal ram area, and the stack depth can be expanded up to 256 bytes. the external data memory can be expanded up to 64 kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. the internal can controller (in C505CA only) and the internal 1 kbyte xram are located in the external memory address area at addresses f700 h to f7ff h and fc00 h to ffff h respectively. the can controller registers and internal xram can therefore be accessed using movx instructions with addresses pointing to the respective address areas. 2.3 general purpose registers the lower 32 locations of the internal ram are assigned to four banks of eight general purpose registers (gprs) each. only one of these banks may be enabled at a time. two bits in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in chapter 2). this allows fast context switching, which is useful when entering subroutines or interrupt service routines. the 8 general purpose registers of the selected register bank may be accessed by register addressing. with register addressing the instruction op code indicates which register is to be used. for indirect addressing r0 and r1 are used as pointer or index register to address internal or external memory (e.g. mov @r0). reset initializes the stack pointer to location 07 h and increments it once to start from location 08 h which is also the first register (r0) of register bank 1. thus, if one is going to use more than one register bank, the sp should be initialized to a different location of the ram which is not used for data storage.
semiconductor group 2-3 memory organization c505a 2.4 special function registers the registers, except the program counter and the four general purpose register banks, reside in the special function register area. the special function register area consists of two portions : the standard special function register area and the mapped special function register area. one special function register of the c505a (pcon1) is located in the mapped special function register area. for accessing the mapped special function register area, bit rmap in special function register syscon must be set. all other special function registers are located in the standard special function register area which is accessed when rmap is cleared (0). in the C505CA, the registers and data locations of the can controller (can-sfrs) are located in the external data memory area at addresses f700 h to f7ff h . this is compatible to the c505c and details about the access of these registers is described in the c505c users manual. special function register syscon (address b1 h ) reset value : xx100x01 b (C505CA only) reset value : xx100001 b as long as bit rmap is set, mapped special function register area can be accessed. this bit is not cleared by hardware automatically. thus, when non-mapped/mapped registers are to be accessed, the bit rmap must be cleared/set respectively by software. all sfrs with addresses where address bits 0-2 are 0 (e.g. 80 h , 88 h , 90 h , 98 h , ..., f8 h , ff h ) are bitaddressable. the 52 special function registers (sfrs) in the standard and mapped sfr area include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. the sfrs of the c505a are listed in table 2-1 and table 2-2 . in table 2-1 they are organized in groups which refer to the functional blocks of the c505a. the can-sfrs (applicable to the C505CA only) are also included in table 2-1 . table 2-2 illustrates the contents of the sfrs in numeric order of their addresses. table 2-3 list the can-sfrs in numeric order of their addresses. bit function cswo can controller switch-off bit cpwd = 0 : can controller is enabled (default after reset). cpwd = 1 : can controller is switched off. this function is an enhancement over the c505c-2r. C reserved bits for future use. read by cpu returns undefined values. 76543210 eale rmap cmod b1 h syscon bit no. msb lsb cswo xmap1 CC xmap0 the functions of the shaded bits are not described here. 1) 1) this bit is available in the C505CA only.
memory organization c505a semiconductor group 2-4 table 2-1 special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl dpsel psw sp syscon 2) vr0 4) vr1 4) vr2 4) accumulator b-register data pointer, high byte data pointer, low byte data pointer select register program status word register stack pointer system control register version register 0 version register 1 version register 2 e0 h 1) f0 h 1) 83 h 82 h 92 h d0 h 1) 81 h b1 h fc h fd h fe h 00 h 00 h 00 h 00 h xxxxx000 b 3) 00 h 07 h xx100x01 b 3) 6) xx100101 b 3) 7) c5 h 05 h 5) a/d- converter adcon0 2) adcon1 addath addatl p1ana 2) 4) a/d converter control register 0 a/d converter control register 1 a/d converter high byte data register a/d converter low byte data register port 1 analog input selection register d8 h 1) dc h d9 h da h 90 h 00x00000 b 3) 01xxx000 b 3) 00 h 00xxxxxx b 3) ff h interrupt system ien0 2) ien1 2) ip0 2) ip1 tcon 2) t2con 2) scon 2) ircon interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 interrupt priority register 1 timer control register timer 2 control register serial channel control register interrupt request control register a8 h 1) b8 h 1) a9 h b9 h 88 h 1) c8 h 1) 98 h 1) c0 h 1) 00 h 00 h 00 h xx000000 b 3) 00 h 00x00000 b 00 h 00 h xram xpage syscon 2) page address register for extended on-chip xram and can controller system control register 91 h b1 h 00 h xx100x01 b 3) 6) xx100101 b 3 7) ports p0 p1 p1ana 2) 4) p2 p3 p4 port 0 port 1 port 1 analog input selection register port 2 port 3 port 4 80 h 1) 90 h 1) 90 h 1) a0 h 1) b0 h 1) e8h 1) ff h ff h ff h ff h ff h xxxxxx11 b 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved 4) this sfr is a mapped sfr. for accessing this sfr, bit rmap in sfr syscon must be set. 5) the content of this sfr varies with the actual step of the c505a (eg. 11 h for the first step) 6) c505a only 7) C505CA only
semiconductor group 2-5 memory organization c505a serial channel adcon0 2) pcon 2) sbuf scon srell srelh a/d converter control register 0 power control register serial channel buffer register serial channel control register serial channel reload register, low byte serial channel reload register, high byte d8 h 1) 87 h 99 h 98 h 1) aa h ba h 00x00000 b 3) 00 h xx h 3) 00 h d9 h xxxxxx11 b 3) timer 0/ timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h compare/ capture unit / timer 2 ccen cch1 cch2 cch3 ccl1 ccl2 ccl3 crch crcl th2 tl2 t2con ien0 2) ien1 2) comp./capture enable reg. comp./capture reg. 1, high byte comp./capture reg. 2, high byte comp./capture reg. 3, high byte comp./capture reg. 1, low byte comp./capture reg. 2, low byte comp./capture reg. 3, low byte reload register high byte reload register low byte timer 2, high byte timer 2, low byte timer 2 control register interrupt enable register 0 interrupt enable register 1 c1 h c3 h c5 h c7 h c2 h c4 h c6 h cb h ca h cd h cc h c8 h 1) a8 h 1) b8 h 1) 00 h 3) 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00x00000 b 3) 00 h 00 h watchdog wdtrel ien0 2) ien1 2) ip0 2) watchdog timer reload register interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 86 h a8 h 1) b8 h 1) a9 h 00 h 00 h 00 h 00 h power save modes pcon 2) pcon1 4) power control register power control register 1 87 h 88 h 1) 00 h 0xx0xxxx b 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. table 2-1 special function registers - functional blocks (contd) block symbol name address contents after reset
memory organization c505a semiconductor group 2-6 can controller (C505CA only) cr sr ir btr0 btr1 gms0 gms1 ugml0 ugml1 lgml0 lgml1 umlm0 umlm1 lmlm0 lmlm1 mcr0 mcr1 uar0 uar1 lar0 lar1 mcfg db0 db1 db2 db3 db4 db5 db6 db7 control register status register interrupt register bit timing register low bit timing register high global mask short register low global mask short register high upper global mask long register low upper global mask long register high lower global mask long register low lower global mask long register high upper mask of last message register low upper mask of last message register high lower mask of last message register low lower mask of last message register high message object registers : message control register low message control register high upper arbitration register low upper arbitration register high lower arbitration register low lower arbitration register high message configuration register message data byte 0 message data byte 1 message data byte 2 message data byte 3 message data byte 4 message data byte 5 message data byte 6 message data byte 7 f700 h f701 h f702 h f704 h f705 h f706 h f707 h f708 h f709 h f70a h f70b h f70c h f70d h f70e h f70f h f7n0 h 5) f7n1 h 5) f7n2 h 5) f7n3 h 5) f7n4 h 5) f7n5 h 5) f7n6 h 5) f7n7 h 5) f7n8 h 5) f7n9 h 5) f7na h 5) f7nb h 5) f7nc h 5) f7nd h 5) f7ne h 5) 01 h xx h 3) xx h 3) uu h 3) 0uuuuuuu b 3) uu h 3) uuu11111 b 3) uu h 3) uu h 3) uu h 3) uuuuu000 b 3) uu h 3) uu h 3) uu h 3) uuuuu000 b 3) uu h 3) uu h 3) uu h 3) uu h 3) uu h 3) uuuuu000 b 3) uuuuuu00 b 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved. u means that the value is unchanged by a reset operation. u values are undefined (as x) after a power-on reset operation 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. 5) the notation n (n= 1 to f) in the message object address definition defines the number of the related message object. table 2-1 special function registers - functional blocks (contd) block symbol name address contents after reset
semiconductor group 2-7 memory organization c505a table 2-2 contents of the sfrs, sfrs in numeric order of their addresses addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h 2) p0 ff h .7 .6 .5 .4 .3 .2 .1 .0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 86 h wdtrel 00 h wdt psel .6 .5 .4 .3 .2 .1 .0 87 h pcon 00 h smod pds idls sd gf1 gf0 pde idle 88 h 2) tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88 h 3) pcon1 0xx0- xxxx b ewpd C C ws C C C C 89 h tmod 00 h gate c/t m1 m0 gate c/t m1 m0 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 90 h 2) p1 ff h t2 clk- out t2ex .4 .3 int5 int4 .0 90 h 3) p1ana ff h ean7 ean6 ean5 ean4 ean3 ean2 ean1 ean0 91 h xpage 00 h .7 .6 .5 .4 .3 .2 .1 .0 92 h dpsel xxxx- x000 b C C C C C .2 .1 .0 98 h 2) scon 00 h sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf xx h .7 .6 .5 .4 .3 .2 .1 .0 a0 h 2) p2 ff h .7 .6 .5 .4 .3 .2 .1 .0 a8 h 2) ien0 00 h ea wdt et2 es et1 ex1 et0 ex0 a9 h ip0 00 h owds wdts .5 .4 .3 .2 .1 .0 aa h srell d9 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set.
memory organization c505a semiconductor group 2-8 b0 h 2) p3 ff h rd wr t1 t0 int1 int0 txd rxd b1 h syscon 3) xx10- 0x01 b C C eale rmap cmod C xmap1 xmap0 b1 h syscon 4) xx10- 0001 b C C eale rmap cmod cswo xmap1 xmap0 b8 h 2) ien1 3) 0000- 00x0 b exen2 swdt ex6 ex5 ex4 ex3 C eadc b8 h 2) ien1 4) 00 h exen2 swdt ex6 ex5 ex4 ex3 ecan eadc b9 h ip1 xx00- 0000 b C C .5 .4 .3 .2 .1 .0 ba h srelh xxxx- xx11 b CCCCCC.1.0 c0 h 2) ircon 00 h exf2 tf2 iex6 iex5 iex4 iex3 swi iadc c1 h ccen 00 h coca h3 coca l3 coca h2 coca l2 coca h1 coca l1 coca h0 coca l0 c2 h ccl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c3 h cch1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c4 h ccl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c5 h cch2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c6 h ccl3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c7 h cch3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c8 h 2) t2con 00x0- 0000 b t2ps i3fr C t2r1 t2r0 t2cm t2i1 t2i0 ca h crcl 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h crch 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 d0 h 2) psw 00 h cy ac f0 rs1 rs0 ov f1 p 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) c505a only 4) C505CA only table 2-2 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
semiconductor group 2-9 memory organization c505a d8 h 2) adcon0 00x0- 0000 b bd clk C bsy adm mx2 mx1 mx0 d9 h addath 00 h .9 .8 .7 .6 .5 .4 .3 .2 da h addatl 00xx- xxxx b .1.0CCCCCC dc h adcon1 01xx- x000 b adcl1 adcl0 C C C mx2 mx1 mx0 e0 h 2) acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 e8 h 2) p4 3) xxxx- xx11 b C C C C C C C C e8 h 2) p4 4) xxxx- xx11 b C C C C C C rxdc txdc f0 h 2) b 00 h .7 .6 .5 .4 .3 .2 .1 .0 fc h 5) 6) vr0 c5 h .7 .6 .5 .4 .3 .2 .1 .0 fd h 5) 6) vr1 05 h .7 .6 .5 .4 .3 .2 .1 .0 fe h 5) 6) vr2 7) .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) c505a only 4) C505CA only 5) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. 6) these are read-only registers 7) the content of this sfr varies with the actual of the step c505a (eg. 11 h for the first step) table 2-2 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
memory organization c505a semiconductor group 2-10 table 2-3 contents of the can registers in numeric order of their addresses (C505CA only) addr. n=1-f h 1) register content after reset 2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f700 h cr 01 h test cce 0 0 eie sie ie init f701 h sr xx h boff ewrn C rxok txok lec2 lec1 lec0 f702 h ir xx h intid f704 h btr0 uu h sjw brp f705 h btr1 0uuu. uuuu b 0 tseg2 tseg1 f706 h gms0 uu h id28-21 f707 h gms1 uuu1. 1111 b id20-18 11111 f708 h ugml0 uu h id28-21 f709 h ugml1 uu h id20-13 f70a h lgml0 uu h id12-5 f70b h lgml1 uuuu. u000 b id4-0 000 f70c h umlm0 uu h id28-21 f70d h umlm1 uu h id20-18 id17-13 f70e h lmlm0 uu h id12-5 f70f h lmlm1 uuuu. u000 b id4-0 000 f7n0 h mcr0 uu h msgval txie rxie intpnd f7n1 h mcr1 uu h rmtpnd txrq msglst cpuupd newdat f7n2 h uar0 uu h id28-21 f7n3 h uar1 uu h id20-18 id17-13 f7n4 h lar0 uu h id12-5 f7n5 h lar1 uuuu. u000 b id4-0 000 f7n6 h mcfg uuuu. uu00 b dlc dir xtd 0 0 1) the notation n (n= 1 to f) in the address definition defines the number of the related message object. 2) x means that the value is undefined and the location is reserved. u means that the value is unchanged by a reset operation. u values are undefined (as x) after a power-on reset operation
semiconductor group 2-11 memory organization c505a f7n7 h db0 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7n8 h db1 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7n9 h db2 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7na h db3 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7nb h db4 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7nc h db5 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7nd h db6 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7ne h db7 xx h .7 .6 .5 .4 .3 .2 .1 .0 1) the notation n (n= 1 to f) in the address definition defines the number of the related message object. 2) x means that the value is undefined and the location is reserved. u means that the value is unchanged by a reset operation. u values are undefined (as x) after a power-on reset operation table 2-3 contents of the can registers in numeric order of their addresses (contd) (C505CA only) addr. n=1-f h 1) register content after reset 2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
s e mic o nduct o r group 3 -1 10-bit a/d converter c505a 3 a/d converter the c505 a includes a high performanc e / hig h speed 10-bit a/d-converte r (adc) with 8 analog input channels. it operat e s with a successive approximati o n technique and uses s e lf calibrati o n mec h anisms for re d ucti o n and compensatio n of offset and linearity errors . the a/d converter provi d es th e followi n g features: C 8 multiplex e d inpu t chann e ls (p o r t 1), w h ich can also be u sed as digital i n puts/o u tputs C 1 0 - b i t r e s o l u t i on C sin g le or continu o us conversion m o de C in t ernal start-of-conversion trigg e r capability C in t errupt request genera t ion aft e r each conv e rsion C using successive approximation c o nversion techniqu e via a capacitor array C built-in hidden calibr a tion o f offset a nd li n earit y errors the e xt e rn a lly a p pli e d r e f e re n ce vo l ta g e r a nge has to be h eld o n a fixed v alue w i thin the specifications. the m a in function a l blocks of the a/d converter are shown i n figure 3-1 . 3.1 a/d converter operation an internal s t art of a single a/d conversion is triggered by a write-to-addatl instruction . the start proced u re itself is inde p endent of the value whic h is written to addatl. w h en sin g le conversi o n m o de i s s e lected ( b it adm=0) only one a/d conversi o n i s p e rformed. in c o ntinu o u s m o de (bit adm=1) , after com p letion o f an a/d conversion a new a/d conversi o n i s triggered automatically until bit adm is reset. the busy flag bsy (adcon0 . 4) i s automatically set when an a/d conversion is in progress. after com p letio n of the conv e rsion it is reset by hardware. this flag ca n be rea d o nly, a writ e has no effect. the interrupt request flag i adc (ircon.0) is se t when an a/d conversion is completed. the bits mx 0 to mx 2 in speci a l functio n register adcon0 a nd adcon1 are used for selectio n of the anal o g input c h annel. the bits mx0 to mx2 are repr e sented in b oth r e gister s adcon0 and adcon1; however, thes e bits are prese n t o n ly onc e . th e r e fore, there are two me t hods of selecti n g a n a nalog inpu t c h annel : i f a ne w ch a nnel is selected in adcon1 th e change is aut o matically do n e in th e corres p ondin g bits mx 0 to mx2 in adcon0 an d vice vers a . p o r t 1 is a dual purp o se inpu t /output port. these pins can be use d e ither for digital i/o fu n ctio n s or as t he an a log inputs. if less tha n 8 an a log inputs are r e quired , the u n use d anal o g in p uts a t por t 1 are free for d igital i/o f uncti o ns.
s e mic o nduct o r group 3 -2 10-bit a/d converter c505a figure 3-1 block diagra m of the a/d converter s ha d e d b i t locati o ns a r e not used in a dc - f u nct i ons. i n t e rn a l b u s m u x ad m mx2 mx 1 mx0 ad c on0 (d8 h ) bs y C p o rt 1 addath (d9 h ) .3 .4 .5 .6 .7 .8 si n gle / conti n uo u s mo d e a / d converter start of c o nversi o n write to addatl inter n al b u s s & h f o s c v ar e f v a g nd bd clk ea n 7 ean 2 ean 1 ean 0 ean 6 ean 5 ean 4 ean3 p 1ana ( 9 0 h ) iex 4 iex3 swi iadc ircon (c0 h ) iex 5 iex 6 exf2 tf2 ex e n2 ex4 ex 3 e c a n ea d c ien1 (b8 h ) ex 5 ex 6 swdt clock ? 32, 16 , 8, 4 prescaler conve r si o n clock f a d c msb .2 C mx2 mx 1 mx0 ad c on1 (dc h ) C C ad c l 1 a d c l0 i n put clock f in addatl (da h ) C C C C C l s b .1 C
s e mic o nduct o r group 3 -3 10-bit a/d converter c505a 3.2 a/d converter registers this section describes the bits/fu n ctio n s of all registers which are used by the a/d converter. special function register addath (address d9 h ) reset value : 00 h special function register addatl (address da h ) reset value : 00xxxxxx b the registers addath and addatl hold the 10-bit conversion result in left justified data format. the most significant bit of the 10-bi t conversion resul t is bit 7 of addath. the leas t significa n t bit o f th e 10-bi t conversion resul t is bit 6 of addatl. t o get a 10-bit conversio n result, both addat re g isters must be r e ad. if an 8 - b it c on v ersion r e sult is re q uire d , o n ly the re a di n g of addath i s necessary. th e data remains in addat un t i l it is overwritte n by the next converted data . addat can be rea d or written under so f twar e control. l f the a/d converter o f the c505a is no t used , register addath can be used as an additional general purpose register. 76543210 d9 h addath l s b da h addatl bit no . msb lsb m s b C C C C CC .9 .8 .7 .6 .5 .4 .3 .2 .1 .0
s e mic o nduct o r group 3 -4 10-bit a/d converter c505a special function register adcon0 (address d8 h ) reset value : 00 h special function register adcon1 (address dc h ) reset value : 01xxx000 b the sha d ed b i ts are n o t us e d f o r a /d conv e rt e r c o ntrol. bit function C res e rved bits for fu t ure use bsy busy flag this flag i n dica t es w h ether a conv e rsion is in progress (bsy = 1). the flag is cleared b y hardware when t h e conversi o n is f inished. adm a/d conversi o n mode whe n set , a c o ntinuo u s a/d conversion is selected . if cleared d uring a runni n g a/d conversi o n, the conversion is st o pped at its en d . mx2 - mx 0 a/d converter input channel select bits bits mx2-0 can be written or read either in adcon0 or adcon1. the channel selection done by writing to adcon 1(0) overwrites the selection in adcon 0(1) whe n adcon 1(0) is written after adcon 0(1). th e analo g inputs are s e lecte d according t h e following table : 76543210 C bsy a d m m x2 m x 1 m x0 d8 h adcon0 adcl1 mx2 mx1 mx 0 dc h a d co n 1 bit no . msb lsb adcl0 cl k bd CC C mx2 mx1 mx0 selecte d analog i nput 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 p1.0 / an0 / int3 / cc0 p1.1 / an1 / int4 / cc1 p1.2 / an2 / int5 / cc2 p1.3 / an3 / int6 / cc3 p1.4 / an4 p1.5 / an5 / t2ex p1.6 / an6 / clkout p1.7 / an7 / t2
s e mic o nduct o r group 3 -5 10-bit a/d converter c505a not e : generally, before entering the power-dow n mod e , an a/d conv e rsio n in progress mus t be st o pped. i f a single a/d c o nversion is running, i t must be terminate d by p olling the bsy bi t or waitin g for th e a/d conversio n interrupt . in continuo u s conversion mode, bit adm mus t be c l e a r e d an d t h e l a s t a/d c o n v ers i on m u s t be term i n ated b ef o re e n t e ri n g t h e p o wer- d own mo d e. a single a/d conversion is started by writin g to sfr addatl wit h dummy data. a continuous conversio n is started u n der the following conditions : C by setti n g bit adm during a running single a/d co n version C by setting bit adm when at least one a/d conversion has occurred after the last reset o p eration. C b y writin g addatl wit h dumm y data after bit adm has been set before (if n o a/d conversion h a s occurred aft e r the last rese t operatio n ). when bit adm is r e set by software in c o ntinuo u s conversio n m o de, the just running a/d conversi o n is stoppe d after its end. adcl1 adcl0 a/d converter clock prescaler s e lection adcl1 and adcl0 select the prescaler ratio for the a/ d conversion clock f adc . depe n ding on t he cl o ck rat e f osc of the c505a, f adc must be a d just e d in a wa y that t h e res u ltin g conversi o n cloc k f adc is less t h an or e qua l to 2 mhz (see section 3 .3). th e presc a ler rati o is selected accordi n g to the f o llowin g table : bit function adcl 1 adcl0 prescaler ratio 0 0 0 1 1 0 1 1 div i de by 4 divide by 8 (defaul t after res e t) div i de by 1 6 div i de by 3 2
s e mic o nduct o r group 3 -6 10-bit a/d converter c505a the a/d converter interrupt is controlled by bits which are located in th e sfrs ien1 an d ircon. special function register ien1 (address b8 h ) reset value : 00 h special function register ircon (address c0 h ) reset value : 00 h the sha d ed b i ts are n o t us e d f o r a /d conv e rt e r c o ntrol. bit function eadc enable a/d converter interrupt if eadc = 0, the a/d converter interrupt is disabled. swi this bit can b e set by software t o generate a n interru p t. the i n terrupt servic e rou t ine is at 00 4 b h . this bit is cleared when t he interru p t is p rocessed. this interrupt is enabled b y setting bit ien1.1(ecan). c7 h c6 h c5 h c4 h c3 h c2 h c1 h c0 h iex6 iex5 iex4 iex3 swi iad c c0 h ir c o n tf 2 exf2 exen 2 swdt ex6 ex 5 b8 h ien1 bit no. bf h m s b lsb ex4 ex3 e c a n ea d c be h bd h bc h bb h ba h b9 h b8 h
s e mic o nduct o r group 3 -7 10-bit a/d converter c505a 3.3 a/d converter clock selectio n the adc uses two clock signals for op e ration : the conversion clock f adc (=1/t adc ) and t he in p ut clock f in (=1/t in ). f adc is d e rived from the c505a system clock f osc which is applied at the xtal pins via the adc cl o ck prescal e r as shown in figure 3-2 . the input clock f in is equal t o f osc the conversion f adc clock is limited to a maximum freq u ency of 2 mhz. theref o re , t h e ad c clock prescaler mus t b e pro g rammed to a value which assures that the conversion cl o ck does n o t e xce e d 2 mhz. the prescaler ratio is selected by the bits adcl1 and adcl0 of sfr adcon1. the tabl e in figure 3-2 shows t h e presc a ler ratio which must be selected by adcl1 and adc l 0 for typical system clock rates. up to 8 mhz sy s tem clock the pres c aler ratio 4 is se l ected. us i ng a system cl o ck greater than 8 mhz a n d l e ss than 16 mhz, the p r e scaler ratio o f at least 8 must b e sel e cted. a prescaler ratio of at least 16 must be sel e cted when using a system clock greater th a n 16 mhz. a prescaler ratio o f 32 ca n used f o r any o f the above freque n cy ra n ges. figure 3-2 a/d converter clock selection the d u r a tio n of a n a/d conversi o n is a multipl e of th e peri o d o f the f in c l ock s i gnal . the calculati o n of the a/d conversion time is shown in t h e nex t section. mcu system clock rate (f osc ) f in [mhz] prescaler ratio f a d c [mhz] adcl1 adcl0 2 mhz 2 ? 4 0.5 0 0 6 mhz 6 ? 4 1.5 0 0 8 mhz 8 ? 4 200 12 mhz 1 2 ? 8 1.5 0 1 16 mhz 1 6 ? 8 201 20 mhz 2 0 ? 16 1.25 1 0 f osc clo c k pres c aler ? 16 c o nversion cl o ck ? 8 ? 4 mux a / d converter adcl1 adcl0 f adc max = 2 mhz condition : f adc ? 32 f in input clo c k f in = 1 clp f osc =
s e mic o nduct o r group 3 -8 10-bit a/d converter c505a 3.4 a/d convers i on timing an a / d conversion is started by writin g into the sfr addatl with dummy data. a write to sfr addat l will start a new c o nversion even if a conversio n is currently in pro g r e ss. t h e conversi o n begins with the n ext machi n e cycle, a nd the bsy flag in sfr adcon 0 will b e set. the a/d conversio n procedur e is divi d ed int o three parts : C sam p le ph a se (t s ), used for sampling the a nalog input voltag e . C conversio n phas e (t co ), used for the real a/d conversion (includes calibra t ion). C wri t e result phase (t wr ), used for writing the conversion result into the addat registers. the t otal a/d conversio n time is defin e d by t adcc which is t he sum of t h e two phase times t s a n d t co . th e d uration of the three phas e s o f a n a/ d conversion is s p ecified by their correspondi n g timing parameter as shown in figure 3-3 . figure 3-3 a/d conversion timing s a mple time t s : during t his tim e the int e rnal capacitor array is co n nected to the selected anal o g i n put channel a n d is loade d with th e analog voltage to be converted. the analog voltag e is inter n ally fed to a volta g e comparator. wit h beginning of the sample phase the bsy bit in sfr adcon0 is set. s a mple p h ase c o nversion p hase s t a r t o f a n a d co n version bsy bit t s t co t wr r e sult is writt e n into addat t adcc a/d conversi o n t i me cycle time write result p h ase prescaler ratio (=ps) t s t co t a dcc 32 64 x t in 320 x t in 38 4 x t in 16 32 x t in 160 x t in 19 2 x t in 8 16 x t in 8 0 x t in 9 6 x t in 4 8 x t in 4 0 x t in 4 8 x t in t adcc = t s + t co t wr = t in p s = p r esc a ler val u e
s e mic o nduct o r group 3 -9 10-bit a/d converter c505a conversion tim e t co : d u ri n g th e co n v e rsion tim e t he a nalog vol t ag e is conver t ed into a 1 0-bit digital value u sing t h e s u ccessive a ppr o ximation t e chniq u e with a bi n ary wei g hted capacitor n etwork. duri n g an a/d conversion also a calibra t ion takes place. duri n g t his calibrati o n alter n ati n g o ffse t a n d lin e arity calibratio n cycles a re executed (s e e also section 3.5) . at t h e end of t h e calibrati o n tim e the bsy bit is reset an d the iadc bit in sfr ircon is set indicating an a/d converter interrupt condition. write result t i me t wr : at the result phase the conversion result is written into the addat registers. figure 3-4 shows how an a/d conv e rsion is emb e dded int o t he microcontroller cycle scheme usi n g the relation 6 x t in = 1 instructio n cycle. i t als o shows the behaviour of the bus y flag (bsy) and the interrup t flag (iadc) during an a/d conversion. figure 3-4 a/d conversion timing in relation to processor cycle s de p en d ing on t h e se l ect e d presc a ler ratio (se e figure 3-2 ), f o ur d ifferent re l ati o ns h ips b e tween m achine cycles and a/d c onversion are possible. the a/d conversion is started when sfr addat l is written with dummy d a ta. this write o p eration may tak e o ne or tw o machine cycles. in figure 3- 4 , the instruction mov addatl,#0 starts the a/d conversion (machine cycle x-1 and x). the total a/d c o nversion (sample, conversion, a n d calibratio n p hase) is finished wit h the end of t h e 8th, 1 6th, 3 2 nd, o r 64th machine cycle afte r the a/d conversio n start. i n th e nex t machin e cycle t h e conversion result is written into t he addat regis t ers and can be read in t he same cycle by an instruc t ion (e.g . mov a,addatl). if continuous conversion is selected (bi t adm set), the next conversio n is started with t he beginning o f the machin e cycle which follows the write result cycle. pr e sc a ler x-1 x 1 2 4 5 7 8 9 m o v a d d a tl , #0 3 10 11 cont. conv. s ingle co n v. w r ite ad d at b sy b i t iadc bit m o v a , a d d a tl 12 first ins t r. o f an interrupt routine x-1 x 1 2 4 5 1 5 1 6 1 7 3 18 19 20 x-1 x 1 2 4 5 3 1 3 2 3 3 3 34 35 36 x-1 x 1 2 4 5 6 3 6 4 6 5 3 66 67 68 adcl1 adcl0 0 0 0 1 1 0 1 1 s e lect i on start of a/d conversion cycle start of next conv e rsion 6 1 instr u ctio n cycle t adcc a/d c o nversi o n cycle (in continuous mode) write r e sult cycle
s e mic o nduct o r group 3 -10 10-bit a/d converter c505a the bsy bit i s se t at the beginning o f the firs t a/d conversio n machin e cycle an d reset a t the begin n ing of th e wri t e resul t cycle. if c o ntinuo u s co n version is selected, bsy is again set with t h e begin n ing of t he machine cycle whic h follow s the write result cycl e . the i nt e rru p t f l ag iadc is s e t at the end of the a/d c o nversi o n. if t h e a/d co n vert e r i n terr u pt i s enabl e d an d the a/d c o nverte r interrup t i s prioritized t o b e serviced imme d iately, th e firs t instructi o n of the i n terrupt servic e r o utine will be execute d in the t h ird machine cycle w h ich f o llows t h e write resul t cycle. iadc must b e reset by sof t ware. de p endin g on the ap p lic a tion, ty p ically there are three met h ods to handle t he a/d conversio n in t h e c5 0 5a. C software delay th e machi n e cycles of the a/d c o nversion are coun t e d a nd the program executes a software d e lay (e. g . nops) before re a ding th e a/d c o nversion res u lt in t h e write result cycle. this is th e fastest met h od to ge t the result of a n a/d c o nversion. C polling bsy bit th e bsy bi t i s polled a nd th e program waits unti l bsy=0 . attention : a p olling jb instructi o n which is tw o mac h ine cycles l o ng, possibly m a y no t r e cognize th e bsy=0 con d itio n during t h e write result cycle in t he con t inuous conversi o n mode. C a/d conversion interru p t after the start of an a/d conversion the a/d converter interrupt is enabled. the result o f the a/d co n version is rea d in th e interru p t servic e routine . if oth e r c5 0 5a interrup t s ar e enabl e d, th e interrupt latency must be regar d ed. therefore , this software met h od is t he sl o west meth o d t o get the result o f an a/d conv e rsion. de p endin g on the oscillator frequency of the c 5 05a a n d t h e selected divider ratio of the conversi o n clock prescaler the tot a l time of a n a/d conversio n is calcula t ed acc o rdin g figure 3-3 a nd table 3- 1. figure 3-5 on the nex t p age shows the minim u m a/d conversi o n time in rela t ion to the oscill a tor frequency f osc . the minimum conversio n time is 6 m s a n d ca n be a chieved a t f osc of 8 o r 16 mhz (or whenever f a d c = 2 mhz). not e : the prescal e r ratios i n table 3-1 are m i nimum val u es. table 4-1 a/d conversion time for dedicated system cloc k rate s f osc [mhz] prescaler ratio ps f a d c [mhz] samp l e time t s [ m s] total conversion tim e t a d cc [ m s] 2 mhz ? 4 0.5 4 24 6 mhz ? 4 1.5 1.33 8 8 mhz ? 4 2 1 6 12 mhz ? 8 1.5 1.33 8 16 mhz ? 8 2 1 6 20 mhz ? 16 1.25 1 .6 9.6
s e mic o nduct o r group 3 -11 10-bit a/d converter c505a figure 3-5 minimum a/d convers i on time in relation to system clock 10 20 30 5 [ m s] t adcc min = 6 m s ? 4 ? 16 t a dcc 4 1 2 1 6 1 8 f o s c [mhz ] 8 1 4 1 0 6 2 20 ? 8
s e mic o nduct o r group 3 -12 10-bit a/d converter c505a 3.5 a/d converter calibration the c505a a/d c o nverter i n cludes h i dden i n ternal cali b ration mec h anisms which ass u re a safe functionality o f the a/d converter according to the dc charact e ristics. the a/d converter calibrati o n is impl e mente d in a way t hat a user program which execut e s a/d conversio n s is not af f ected b y its operati o n . f u r t her , t h e user program has no co n trol over the calibratio n m e chanism. the calibrati o n itself ex e cutes tw o basic functions : C offset calibratio n : correction o f offset e rr o rs of comparat o r and the capacitor network C l inearity calibrati o n : correction o f the bi n ary weight e d cap a citor n etwork the a/d convert e r cali b ration o p er a tes in two p has e s : calibrat i on after a reset operat i on and calibratio n a t each a/d conversion . th e calibrati o n p h ases ar e co n trolle d by a st a te machine in t h e a/ d converter. this stat e machine e xec u te s the calibr a tio n phases an d st o res t h e calibration r e sults dynamically in a small calibratio n ram. af t er a r e set operation the a/d calibration is autom a tically started. this reset c a libration phase which t akes 332 8 f adc clocks, alternati n g offset an d lin e arit y calibratio n i s executed . therefore , at 8 mh z oscillat o r frequency a nd with t he def a ult af t er rese t prescaler valu e of 4 , a res e t calibrati o n tim e of ap p rox. 1 .66 ms is reached. f o r achievi n g a p roper reset c a libration, t h e f adc pr e scaler val u e must satisfy the condition f adc max 2 mhz. i f thi s conditio n is n o t met a t a s p ecifi c oscill a tor frequency with the d efault prescaler val u e after res e t, the f adc prescaler must be a d just e d immediately a f ter reset b y setting bits adcl1 an d adcl0 in sfr adcon1 to a suitable value . it is als o recomm e nded to have the pro p e r voltag e s, as specifi e d in the dc specifications, appli e d a t t h e v aref and v a r ef pins b e fore the reset calibration has started. af t e r the reset calibration phas e the a/ d convert e r is calibrated according t o its dc characteristics. neverthel e ss, d uring t h e reset calibration phase single or continu o us a/d can be ex e cuted. in this cas e it must be regarded t h at the reset cali b ration is interru p ted and c o ntinue d a fter the end of t h e a/d conversion . therefor e , in t errupting the r e set calibration phas e by a/ d co n versions exten d s t h e tota l r e set cali b ratio n time . if the specifie d tota l unadjusted e rr o r (tue) has to b e valid f o r an a/d conversio n , it is rec o mmend e d to start the first a/d conversio n s after reset when the reset calibratio n phase is finished . depending o n the oscillato r frequency used, t h e rese t calibrati o n phas e ca n b e possibly shortene d b y se t tin g adcl1 a nd adc l 0 (prescal e r value) t o its fina l val u e immediately aft e r r e set. af t er the reset calibr a tion, a second calibr a tion mecha n is m i s initiated. t h is cali b ratio n is coupl e d to each a/ d conversio n . wit h this second calibrati o n mech a nism alternatively o ffset and linearity calibratio n values, store d in the calibration ram, are a lways checked w h en an a/d conversi o n is executed an d correc t ed if req u ired.
s e mic o nduct o r group 3 -13 10-bit a/d converter c505a 3.5.1 a/d converter analog input selectio n th e anal o g inputs a r e locate d a t p ort 1 . t h e corres p ondin g pin s hav e a p or t struct u re , whic h allows to use the m eithe r as digital i/ o pin s or a s analo g inputs (se e section 6 .1.3.2). th e analog in p ut function o f these digital/anal o g por t lin e s a r e s e lect e d via t h e registe r p1ana. this re g iste r lies in th e mapped sfr area and ca n b e accessed whe n bi t rmap in sfr syscon is se t when writing to its address (90 h ). i f a sp e cific bit locatio n of p1ana is s e t, the corresp o ndin g port line is configured as a digital input. wit h a 0 i n the bit location the p ort li n e operates as a n alog p ort. special function registers p1ana (address 90 h ) reset value : ff h bit function ean7 - ean 0 enable analog port 1 inputs i f ean x ( x = 7-0) is cleared , por t pi n p1. x is enabled for operation as an analog input. if eanx is set, port pin p1.x is e nable d for digital i/o f u ncti o n (default after reset). 76543210 90 h p1ana bit no . msb lsb ean7 ea n 6 ea n 5 ea n 4 e a n3 e an2 ean1 ean0
s e mic o nduct o r group 4- 1 otp memory operation c505a 4 otp memory operatio n th e c505a-4e is the otp versio n in the c5 0 5a micr o controller with a 32k byt e one-time programmable (otp ) p rogram mem o ry. wit h t h e c505a-4e fast programming cycles are achiev e d (1 byte in 100 m sec). also several levels of otp mem o ry prot e ction can be selected. t h e b asic functionality of the c505a-4 e as microcontrolle r is identical to the c505a-l (romless part) functionality. 4.1 programming conf i guration during norm a l program executio n the c505a-4e behaves like th e c5 0 5 a- l . for programming t h e device , the c505a-4e mus t be p u t in t o th e programmin g mod e . this, typic a lly, is don e no t in-system but i n a specia l programming hardware . in th e pro g ramming m o de the c505a-4 e operates a s a slave device similar as a n eprom st a ndalo n e memory d e vic e a nd must be controlled wit h a ddress/ data i n formation, co n trol lines, a n d an external 1 1 .5 v programming voltag e . in the pro g r a mmi n g m ode p o rt 0 p r o vi d es the bi d irecti o n a l d a ta li n es a nd port 2 is u s e d f o r the multiplexed address inputs . t h e u pper address inform a tion at port 2 is l a tched with the signal pale. for basic programming mode selection the inputs reset, psen , ea /v pp , ale and pmsel1/0 and p s el are used. further, the inputs pmsel1,0 are required to select the access types (e.g. program/verify data, writ e lock bits, ....) in th e programming mode. i n programming mode v cc /v ss and a clock signal at the xtal pins must be applied to the c505a-4e. the 11.5 v external programming voltage is input throu g h the ea /v pp pin. fi g ure 4-1 show s the pins o f the c505a-4 e which ar e required for controllin g of th e otp programming mode. figure 4-1 programming mode configuration port 0 p0.0-7 v cc v ss c505a-4e C505CA-4e prog p2.0-7 port 2 ea / v pp pmsel0 psel re s et psen pmsel1 prd pale xtal1 xtal2
otp memory operation c505a s e mic o nduct o r group 4 -2 4.2 pin configuration figure 4-2 sh o ws the detailed pin co n figuration of th e c5 0 5a-4e in programming mode. figure 4-2 otp programmin g mode pin conf i guration (top view) d4 d5 d6 d7 ea / v pp n.c. a5 / a1 3 pr o g a6 / a1 4 a7 ps en a 4 / a 1 2 a 3 / a 1 1 a 2 / a 1 0 a 1 / a 9 a 0 / a8 v cc x t a l 1 x t a l 2 n.c. n.c. v ss 33 34 35 36 37 38 39 40 41 42 43 44 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 23 22 21 20 19 18 17 16 15 14 13 12 12345 6 7 8 9 1 0 11 c505a-4e d3 d2 d1 n.c. n.c. n.c. n.c. n.c. n.c. d0 n.c. n. c. n. c. n. c. re s e t pm se l0 pm se l1 ps el pr d pa le n. c. n. c. C505CA-4e
s e mic o nduct o r group 4 -3 otp memory operation c505a 4.3 pin definitions the following figure 4-1 contains th e functiona l descripti o n of a ll c505a-4e p in s which a r e requir e d for otp m e mory pr o gramming table 4-1 pin definitions and functions of the c505a-4e in programm i ng mode symbol pin numbe r i/o * ) function p-mqfp-44 reset 4 i reset this inpu t must b e at s t atic 1 ( a ctive) level during the whol e programming mode. p m sel0 p m sel1 5 7 i i programmin g mode selection p i ns these pins are us e d to s e lect t he diff e r e nt access modes in programming m o de . pmsel1, 0 must satisfy a setu p time t o t he rising ed g e of pale . when the logic lev e l of pmsel1,0 is ch a nged, pale must be at low level. psel 8 i basic programming mode se l ect this inpu t is used for t h e basic programmin g mode selection and must b e switch e d according figure 4- 3 . p r d 9 i programmin g mode read strobe this inp u t is u sed f o r read access co n trol for otp memory read, version byte read , and lock bit read op e r a tions. pale 10 i programmin g address latch enable pa l e is use d to latc h the high address lines. the high address lines must satisfy a setu p an d hold t im e to/from t he fallin g edge of pale. pale must b e at low level when the logic level of pmsel1,0 is cha n ged. xtal2 14 o xtal2 ou t put of th e inv e r t ing oscillator amplifier. xtal1 15 i xtal1 inpu t to the oscillator amplifier. * ) i = in p ut o = output pmsel1 pmsel0 access mode 0 0 r e s e r v e d 0 1 re a d si g nature bytes 1 0 pro g ram/read lock bits 1 1 pro g ram/read otp mem o ry byte
otp memory operation c505a s e mic o nduct o r group 4 -4 v ss 16 C circu i t groun d potential must be ap p lied in programmin g mode. v cc 17 C power supply terminal must be ap p lied in programmin g mode. p 2 .0 - 7 1 8 - 2 5 i address lines p2.0- 7 are used as multiplexe d addres s inpu t lin e s a0-a 7 and a8-a14. a8-a14 must be latche d wi t h pale. psen 26 i program store e n able this inpu t must b e at s t atic 0 level durin g the whole programming mode. p r og 27 i programmin g mode write strobe this inpu t is used i n programming m o de a s a write strob e for otp m e mory p r o gram, an d lock bit writ e operati o ns during basic pro g r a mmi n g mod e selection a low level must be ap p lied to prog . ea /v pp 29 C programming voltage this pin must be at 11.5 v (v pp ) v o ltage level during programmin g of an otp memory byte or lock bit. durin g an otp memory read operation this pin must be at v ihx h i gh le v el. this p in is also used for basic programming mod e selection. at basic pro g r a mmi n g mod e selection a low level must be ap p lied to ea /v pp . p0.7-0 30-37 i/o data lines 0-7 during pro g ramming mod e , data bytes ar e transferre d via t h e bidirectional d7-0 lines which are located at port 0. n.c. 1-3 , 6, 11-13, 28, 38-44 C not connected these pins should not b e conn e cted in programming mode. * ) i = in p ut o = output table 4-1 pin definitions and functions of the c505a-4e in programm i ng mod e (contd ) symbol pin numbe r i/o * ) function p-mqfp-44
s e mic o nduct o r group 4 -5 otp memory operation c505a 4.4 programming mode selection the selection for th e otp programming mode c a n be separated into two dif f erent parts : C basic pro g ramming mod e sel e ction C access mode selection with the b asic programming mode s e lection the d evice is put int o the mo d e in which it is possible to access t he otp memory throug h the programming interfac e logic. further, aft e r selection of t h e basic programming mode, otp memory access e s ar e e xec u ted by usi n g o n e o f th e access modes. these access modes are otp memory byte program/re a d , versi o n byte read, and program/re a d lock byt e operati o ns. 4.4. 1 basic programming mod e se l ection the basic pr o gramming mod e sel e ctio n sch e me is shown in figure 4- 3 . figure 4-3 basic programming mode selection r e set psen prog ea /v pp 1 0 psel 0 v cc c l ock (xtal1/xtal2) 5v sta b le prd pale 1 0 r e ady f o r a c c e ss mode s election duri n g t h is p e riod si g nals are n o t a ctively driven 0v v i h 2 v pp pmsel1,0 0,1
otp memory operation c505a s e mic o nduct o r group 4 -6 the basic pr o gramming mod e is selected by executing t h e following ste p s : C with a stabl e v cc a clock signal is applied t o t h e xta l pins; t h e rese t pin is se t t o 1 level and the psen pin i s set to 0 level. C p r o g , pale, pmsel1 and ea /v pp are set to 0 level; prd , psel , and pmsel0 ar e set to 1 level. C psel is switch e d from 1 to 0 lev e l and t h ereafter prog is swi t ched t o 1 lev e l. C pmsel1, 0 can no w be changed ; after ea /v pp has be e n set t o v ihx high level o r to v pp the otp memory is ready for access. the pins reset and psen must stay a t 1 respectively 0 static sign a l level during the whole programming mo d e. with a falling edg e o f psel the lo g ic s t ate of prog and ea /v pp is int e rnally latc h ed. these two signals a r e n o w used as programming write pulse signal (prog ) and as programming voltage input pin v pp . after the falling edge of psel , psel must stay at 0 state during a ll pro g ramming operations. note : i f protection level 1 to 3 has bee n programme d (se e sectio n 4.6) a nd th e programmin g mo d e has been left, it is no more possible to ent e r the programmin g mode ! 4.4. 2 otp memory access mode selection when t h e c505a-4e h a s b een p u t i n to th e programmin g mod e usin g the b a sic programmin g mo d e s elect i on, several access m odes of the otp me m ory programm i ng interface are availab l e. the conditions for the different control signals of t hese access m o des are list e d in table 4-2 . the access modes from t h e table ab o ve are basically s e lecte d b y setting the two pmsel1 , 0 lines to the req u ired l o gic level. the prog and prd signal are t he write and re a d strob e sig n al. data is transferre d vi a port 0 and a ddresses are a ppli e d to port 2 . the following sectio n s describes the d e tails of the d ifferent a ccess m o des. table 4-2 ac c ess mode s s e lection ac c ess mode ea / v pp p r og prd pmsel address (port 2) data (port 0) 10 program otp memory byte v pp h h h a0-7 a8-14 d0-7 read otp memory byte v i h x h pro g ram otp loc k bits v pp hhl C d 1 , d 0 s e e table 4-3 re a d otp lock bits v i h x h r e ad o tp v e r s i o n b y te v i h x h l h byt e addr. of versio n byte d0-7
s e mic o nduct o r group 4 -7 otp memory operation c505a 4.5 program / read otp memor y bytes the pro g ram/read otp memory byt e access mo d e is defined by pmsel1, 0 = 1,1. it is i n itiat e d wh e n th e pmsel 1 ,0 = 1, 1 i s valid a t the risin g edg e of pale. wit h th e falling ed g e o f pale t h e upper addresses a 8 -a14 of the 1 5 - b it otp memory address are latched. after a8-a 1 4 has be e n latc h ed, a0-a 7 is put o n t he address bus (p o r t 2 ) . a0-a7 m u st be st a ble when prog is low or prd is low . if su b seque n t otp addres s locations ar e accessed wit h consta n t addr e ss information a t t h e high a ddress lines a8-14, a8-a14 m u st only be latche d once (p a ge address m e chanism). figure 4-4 sh o ws a typica l basic otp memory p rogramming cycl e with a following otp memory read operation. in this example a0-a14 of the read operation are identical to a8-a14 of the precee d ing pro g r a mmi n g operation. figure 4-4 programming / verify otp memory access waveform i f t h e ad d ress li n es a 8 -a1 4 m u s t b e u p dated, pale mus t be ac t ivate d for the latching of th e n e w a8- a 1 4 value. control , a d dress , a n d d a ta inform a tion mus t o nly be switched w h en the prog and prd sig n als are at hig h level . th e pal e h igh pulse must always be executed if a diff e rent acc e ss mo d e has b e en us e d prior to t he act u al access mode . p r og pale port 0 a8- pmsel1,0 1, 1 d0-d7 port 2 a0-a7 a14 prd d0-d7 min. 100 m s min. 1 00 ns
otp memory operation c505a s e mic o nduct o r group 4 -8 figure 4- 5 shows a waveform example of t he pr o gram/read mod e access f o r several otp memory bytes . i n this example otp memory locations 3fd h to 400 h a r e pro g r a mmed . there a fter , otp memory locations 400 h and 3fd h are read. figure 4-5 typical otp memory programming / verify access waveform prog pale p m sel1,0 1, 1 port 2 p r d 03 fd 3fd da t a 1 fe d a ta 2 3fe ff d at a 3 3ff 04 00 4 0 0 00 400 03 fd 3fd da t a 4 da t a 4 da t a 1 port 0
s e mic o nduct o r group 4 -9 otp memory operation c505a 4.6 lock bits programming / read the c505a-4e h as t w o programmabl e lock bit s which , wh e n programme d accordin g table 4-3 , provi d e four l e vels of protection f or the on-chip otp code memory . note : a 1 means that the lock bit is unpro g r a mmed . 0 means that loc k bit is programmed. for a otp verify operation at p r o tection level 1 , the c505a-4e must be p ut int o the otp verificati o n mode. if a device is programmed with pro t ectio n lev e l 2 or 3, it is no longer possible to v e rify th e otp conte n t of a customer rejec t ed (far) otp device. when a protection level h as been activat e d b y programming of the lock bits, th e basic pro g r a mmi n g mode must b e lef t for activation of t h e protection mechanisms. this mea n s, aft e r the activa t ion o f a protection level further otp program/verify o p erations ar e still p ossible if the basic pro g r a mmi n g mode i s m a intai n ed. the state of the lock bits can always b e rea d if pr o tecti o n level 0 is selected. if protec t ion level 1 to 3 has bee n programme d and th e programmin g mod e ha s bee n left , it is n o t possible t o re-enter t h e programming mode. in t h is case, t h e lock bits can n ot be rea d anym o re. figure 4- 6 shows th e waveform of a lock bit write/read a ccess. for a simple drawing, the prog pulse is shortene d . in reality, f o r lock bit pro g ramming, a 10 0 m s prog low pulse must be applied. table 4-3 lock bit protection types lock bits at d1,d0 protection level protection type d1 d 0 1 1 leve l 0 th e otp loc k featur e is d isa b led. duri n g norm a l op e r a tio n of the c505a-4e, the state of the ea pi n is no t latc h ed on reset. 1 0 leve l 1 during normal operatio n of the c505a-4e, movc instructions execut e d from external p rogram m e mory a r e dis a bled from fetchin g cod e by t es fr o m i n terna l memory. ea is s a mple d and latche d on reset . a n otp memory read o peratio n is o n ly possi b le accordi n g to otp verificatio n mode. furt h er pro g r a mmi n g of the otp memory is disa b led (reprogramming security). 0 1 level 2 sam e as l e vel 1 , but also otp memor y r e ad operation using otp verificati o n mode is disabled. 0 0 level 3 sam e as l e vel 2 ; but addition a ll y external cod e execution b y setting ea =low duri n g norm a l op e r a tion o f the c505a-4e is no more possibl e . ext e r n al c o de ex e cuti o n, w h ich is i n itiat e d by a n internal pro g r a m (e.g. by an internal jump instruction a b ove th e otp memory b oundary) , is still possible.
otp memory operation c505a s e mic o nduct o r group 4 -10 figure 4-6 write/read lock b i t w aveform prog pmsel1,0 1, 0 p r d p o r t 0 ( d 1, d 0) 1,0 1 , 0 pale th e exam p l e s h ows the p ro g ramming a n d r e adi n g of a p rotectio n lev e l 1 .
s e mic o nduct o r group 4 -11 otp memory operation c505a 4.6. 1 access of versio n bytes the c50 5 a-4e and C505CA-4e provide three version bytes at address locations fc h , fd h , a n d fe h . t h e in f ormati o n st o r e d i n the versi o n bytes , is d efine d b y the mas k of each microcontroller step , therefore , the versi o n by t es can b e read b ut no t written. th e thre e v e rsio n re g isters hold inform a tion as man u facturer code, d e vice type , and st e pping code. fo r re a ding of the version bytes the con t r o l lines must be used acc o r d in g table 4-2 and figure 4-7 . the addr e ss o f the versio n byte must b e applied a t the port 1 address lines. pale must not b e activated. figure 4-7 read versio n register(s) waveform v e rsion b yte s are typically used by p r o gramming systems for ad a pting t h e programming firmware to sp e cific device charac t eristics such a s otp size e tc. not e : the 3 versi o n bytes are im p leme n ted in a way that they can b e also b e read during normal program e x ecution mode as a mapped register with bit rmap in sf r syscon s et. the a d dr e sses of the v e rsi o n bytes in n o rm a l mode a nd pro g ram m ing m o de are id e nti c al and theref o r e they a re loc a ted in t he sfr a ddress range. the st e ppings of the c505a versi o ns will contain the f o llowin g version byt e information : note: future s t eppings of c505a would h ave a d ifferent version byt e 2 con t ent. stepp i ng version byte 0 = vr0 (mapped addr. fc h ) version byte 1 = vr1 (mapped addr. fd h ) version byte 2 = vr2 (mapped addr. fe h ) es-aa steps of c 5 0 5 a -4e a n d C505CA-4e c5 h 05 h 11 h p r og p m sel1 , 0 0, 1 port 2 prd fc fd fe v r 0 v r 1 port 0 v r 2 pale
otp memory operation c505a s e mic o nduct o r group 4 -12 4.7 otp verificat i on mode th e ot p v e rific a tion mode as shown i n figure 4-8 is use d to verify th e cont e nt s of th e ot p wh e n the protection lev e l 1 h a s been set. the det a iled timing ch a r a cteristics o f t h e otp verification mo d e are sh o wn in the ac specifications (cha p ter 5). figure 4-8 otp verification mod e otp verificati o n mode is selec t ed if the inputs psen , ea , and a l e are put to the sp e cified logic lev e ls. with reset going in a ctive , t h e ot p verification mo d e sequenc e is started . the c505a-4e outputs an ale signal wit h a peri o d of 3 clp an d expects da t a bytes at p o r t 0. the d ata by t es at p ort 0 are assig n ed to the otp addresses in the f o llowin g way : 1 . dat a byt e = cont e nt of otp a d dress 0000 h 2 . dat a byt e = cont e nt of otp a d dress 0001 h 3 . dat a byt e = cont e nt of otp a d dress 0002 h : 1 6 . da t a byt e = cont e nt of otp a d dress 000f h : the c50 5 a-4e does not outpu t any a d dress in f ormatio n during t he otp v e rification mod e . the first dat a byt e to b e v e rifie d is always t h e byte which is a ssigne d to th e ot p address 0 000 h an d must be put onto the data b u s wit h t he falling edge of reset. with eac h f o llowing ale puls e t he otp address pointer is internally incremen t ed and the exp e cted data byte fo r t he next otp address must be delivere d externally. between two ale pulses the dat a at port 0 i s latched (at 3 clp after ale rising edge) and compared internally with the otp content of the a ctual ad d r e ss. if a verify error is detected, the e rr o r c o nditi o n inputs : ale = v ss psen = v ih , ea = v i h 2 reset = r e set ale port 0 p3.5 da t a for data f or low : verify error high : veri f y ok ad d r. x 16 d a ta f or a d. x 1 6 + 1 ad d r. 0 data for a d dr. 1 d a ta f or a d. x 16 -1 1 . a l e p u lse aft e r reset latch latch l a tch l a t c h 6 clp 3 clp
s e mic o nduct o r group 4 -13 otp memory operation c505a i s store d intern a lly . after each 1 6 th dat a byt e th e cum u late d verify result (p a s s or fail) o f the last 1 6 verify o p erations is outpu t at p3. 5 . thi s means tha t p3. 5 stay s at static l e ve l (low f o r fail a nd hig h for pass ) d u ring the tim e when the following 16 bytes are checked. in otp verific a tion mod e , t h e c5 0 5 a- 4 e must b e provi d ed with a syst e m clock a t the xtal pins. figure 4- 9 s h ows a n a p plication ex a mple of an ext e rnal circuitry whic h allows to verify t h e otp, with protection lev e l 1, inside the c 5 05a-4e in t h e ot p verificati o n mode. with reset goi n g inactive , the c505a-4e starts the otp verify sequ e nce. its ale is clockin g a 15-bi t address cou n ter. this counter g enerates the addr e sses for an external eprom which is programmed with t h e conte n ts of th e otp. the verify d e tect logic typically displ a ys the pass/fail inf o rmatio n of the verify operati o n. p3.5 c a n be la t ched wit h the falling e d ge of ale. when th e last byt e of the otp has been handled, the c50 5 a-4e starts g e nerating a psen signal. thi s sig n al or t h e cy sign a l of t he address counter indicate t o the v e rify d etect logic the e nd of t h e otp verifica t ion. figure 4-9 otp verification mode - external circuitry example address & & v cc c505a-4e counter verify det e ct logic p3 . 5 a l e re s et port 0 ea a0-a14 d0-d7 cs oe compare code rom clk s v cc 15-bi t 2 k carry psen
semiconductor group 5-1 device specifications c505a 5 device specifications 5.1 absolute maximum ratings ambient temperature under bias ( t a ) .............................................................. C 40 c to + 125 c storage temperature ( t st )................................................................................C 65 c to + 150 c voltage on v cc pins with respect to ground ( v ss ) ............................................C 0.5 v to 6.5 v voltage on any pin with respect to ground ( v ss ) ..............................................C 0.5 v to v cc +0.5v input current on any pin during overload condition..........................................C 10 ma to + 10 ma absolute sum of all input currents during overload condition ..........................| 100 ma | power dissipation.............................................................................................tbd note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during overload conditions ( v in > v cc or v in < v ss ) the voltage on v cc pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings.
device specifications c505a semiconductor group 5-2 5.2 dc characteristics v cc = 5v +10%, -15%; v ss =0v t a =0 to 70 c for the sab- versions t a = -40 to 85 c for the saf- versions t a = -40 to 110 c for the sah- versions t a = -40 to 125 c for the sak- versions notes see next page parameter symbol limit values unit test condition min. max. input low voltages all except ea , reset ea pin reset pin v il v il1 v il2 C0.5 C0.5 C0.5 0.2 v cc - 0.1 0.2 v cc - 0.3 0.2 v cc + 0.1 v v v C C C input high voltages all except xtal1, reset xtal1 pin reset pin v ih v ih1 v ih2 0.2 v cc +0.9 0.7 v cc 0.6 v cc v cc + 0.5 v cc + 0.5 v cc + 0.5 v v v C C C output low voltages ports 1, 2, 3, 4 port 0, ale, psen v ol v ol1 C C 0.45 0.45 v v i ol = 1.6 ma 1) i ol = 3.2 ma 1) output high voltages ports 1, 2, 3, 4 port 0 in external bus mode, ale, psen v oh v oh2 2.4 0.9 v cc 2.4 0.9 v cc C C C C v v v v i oh =C80 m a i oh =C10 m a i oh = C 800 m a i oh =C80 m a 2) logic 0 input current ports 1, 2, 3, 4 i il C10 C70 m a v in =0.45v logical 0-to-1 transition current ports 1, 2, 3, 4 i tl C 65 C 650 m a v in =2v input leakage current port 0, an0-7 (port 1), ea i li C 1 m a0.45< v in < v cc pin capacitance c io C10pf f c =1mhz, t a =25 c overload current i ov C 5ma 3) 4) programming voltage v pp 10.9 12.1 v 11.5 v 5% 5) supply current at ea / v cc 30 ma 5)
semiconductor group 5-3 device specifications c505a power supply current notes : 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v cc specification when the address lines are stabilizing. 3) overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin exceeds the specified range (i.e. v ov > v cc + 0.5 v or v ov < v ss - 0.5 v). the supply voltage v cc and v ss must remain within the specified limits. the absolute sum of input currents on all port pins may not exceed 50 ma. 4) not 100% tested, guaranteed by design characterization. 5) only valid in porgramming mode. 6) i cc (active mode) is measured with: xtal1 driven with t r / t f = 5 ns, 50% duty cycle , v il = v ss +0.5v, v ih = v cc C 0.5 v; xtal2 = n.c.; ea = port0 = reset = v cc ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (approx. 1 ma) 7) i cc (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t r / t f = 5 ns, 50% duty cycle, v il = v ss +0.5v, v ih = v cc C 0.5 v; xtal2 = n.c.; reset = ea = v ss ; port0 = v cc ; all other pins are disconnected; 8) i cc (active mode with slow-down mode) is measured : tbd 9) i cc (idle mode with slow-down mode) is measured : tbd 10) i pd (power-down mode) is measured under following conditions: ea =port 0= v cc ; reset = v ss ; xtal2 = n.c.; xtal1 = v cc ; v agnd = v ss ; v aref = v cc ; all other pins are disconnected. 11) the typical i cc values are periodically measured at t a = +25 c but not 100% tested. 12) the maximum i cc values are measured under worst case conditions ( t a = 0 c or -40 c and v cc =5.5v) parameter symbol limit values unit test condition typ. 11) max. 12) c505a active mode 12 mhz 20 mhz i cc i cc tbd tbd tbd tbd ma 6) idle mode 12 mhz 20 mhz i cc i cc tbd tbd tbd tbd ma 7) active mode with slow-down enabled 12 mhz 20 mhz i cc i cc tbd tbd tbd tbd ma 8) idle mode with slow-down enabled 12 mhz 20 mhz i cc i cc tbd tbd tbd tbd ma 9) power down current i pd tbd 60 m a v cc = 2..5.5 v 10)
device specifications c505a semiconductor group 5-4 icc diagram c505a : power supply current calculation formulas note : f osc is the oscillator frequency in mhz. i cc values are given in ma. parameter symbol formula active mode i cc typ i cc max tbd tbd idle mode i cc typ i cc max tbd tbd active mode with slow-down enabled i cc typ i cc max tbd tbd idle mode with slow-down enabled i cc typ i cc max tbd tbd i cc [ma] i cc max i cc typ 5 10 15 20 25 30 f osc [mhz] 12 8 420 16 tbd c505a
semiconductor group 5-5 device specifications c505a 5.3 a/d converter characteristics v cc =5v + 10%, C 15%; v ss =0 v t a =0 to 70 c for the sab-c505a versions t a = C 40 to 85 c for the saf-c505a versions t a = C 40 to 110 c for the sah-c505a versions t a = C 40 to 125 c for the sak-c505a versions 4 v v aref v cc + 0.1 v ; v ss C 0.1 v v agnd v ss + 0.2 v notes see next page. clock calculation table : further timing conditions : t adc min = 500 ns t in = 1 / f osc = t clp parameter symbol limit values unit test condition min. max. analog input voltage v ain v agnd v aref v 1) sample time t s C 64 x t in 32 x t in 16 x t in 8 x t in ns prescaler ? 32 prescaler ? 16 prescaler ? 8 prescaler ? 4 2) conversion cycle time t adcc C 384 x t in 192 x t in 96 x t in 48 x t in ns prescaler ? 32 prescaler ? 16 prescaler ? 8 prescaler ? 4 3) total unadjusted error t ue C 2lsbv ss +0.5v v ain v cc -0.5v 4) C 4lsbv ss < v ain < v cc +0.5v v cc - 0.5 v < v ain < v cc 4) internal resistance of reference voltage source r aref C t adc / 250 - 0.25 k w t adc in [ns] 5) 6) internal resistance of analog source r asrc C t s / 500 - 0.25 k w t s in [ns] 2) 6) adc input capacitance c ain C50pf 6) clock prescaler ratio adcl1, 0 t adc t s t adcc ? 32 1 1 32 x t in 64 x t in 384 x t in ? 16 1 0 16 x t in 32 x t in 192 x t in ? 8 0 1 8 x t in 16 x t in 96 x t in ? 4 0 0 4 x t in 8 x t in 48 x t in
device specifications c505a semiconductor group 5-6 notes: 1) v ain may exeed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 2) during the sample time the input capacitance c ain must be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 3) this parameter includes the sample time t s , the time for determining the digital result and the time for the calibration. values for the conversion clock t adc depend on programming and can be taken from the table on the previous page. 4) t ue is tested at v aref = 5.0 v, v agnd = 0 v, v cc = 4.9 v. it is guaranteed by design characterization for all other voltages within the defined voltage range. if an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma, an additional conversion error of 1/2 lsb is permissible. 5) during the conversion the adcs capacitance must be repeatedly charged or discharged. the internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. the maximum internal resistance results from the programmed conversion timing. 6) not 100% tested, but guaranteed by design characterization.
semiconductor group 5-7 device specifications c505a 5.4 ac characteristics (12 mhz, 0.5 duty cycle) v cc = 5v +10%, -15%; v ss =0v t a =0 to 70 c for the sab-c505a versions t a = -40 to 85 c for the saf-c505a versions t a = -40 to 110 c for the sah-c505a versions t a = -40 to 125 c for the sak-c505a versions ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c505a to devices with float times up to 37 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 12 mhz clock 0.5 duty cycle variable clock 1/clp = 2 mhz to 12 mhz min. max. min. max. ale pulse width t lhll 43 C clp - 40 C ns address setup to ale t avll 17 C clp/2 - 25 C ns address hold after ale t llax 17 C clp/2 - 25 C ns ale to valid instruction in t lliv C 80 C 2 clp - 87 ns ale to psen t llpl 22 C clp/2 - 20 C ns psen pulse width t plph 95 C 3/2 clp - 30 Cns psen to valid instruction in t pliv C 60 C 3/2 clp - 65 ns input instruction hold after psen t pxix 0C0 C ns input instruction float after psen t pxiz *) C 32 C clp/2 - 10 ns address valid after psen t pxav *) 37 C clp/2 - 5 C ns address to valid instruction in t aviv C 148 C 5/2 clp - 60 ns address float to psen t azpl 0C0 C ns
device specifications c505a semiconductor group 5-8 ac characteristics (12 mhz, 0.5 duty cycle, contd) external data memory characteristics parameter symbol limit values unit 12 mhz clock 0.5 duty cycle variable clock 1/clp = 2 mhz to 12 mhz min. max. min. max. rd pulse width t rlrh 180 C 3 clp - 70 C ns wr pulse width t wlwh 180 C 3 clp - 70 C ns address hold after ale t llax2 56 C clp - 27 C ns rd to valid data in t rldv C 118 C 5/2 clp- 90 ns data hold after rd t rhdx 0C0Cns data float after rd t rhdz C63C clp - 20ns ale to valid data in t lldv C 200 C 4 clp - 133 ns address to valid data in t avdv C 220 C 9/2 clp - 155 ns ale to wr or rd t llwl 75 175 3/2 clp - 50 3/2 clp + 50 ns address valid to wr t avwl 70 C 2 clp - 97 C ns wr or rd high to ale high t whlh 17 67 clp/2 - 25 clp/2 + 25 ns data valid to wr transition t qvwx 5Cclp/2 - 37C ns data setup before wr t qvwh 170 C 7/2 clp - 122 C ns data hold after wr t whqx 15 C clp/2 - 27 C ns address float after rd t rlaz C0C0ns external clock drive characteristics parameter symbol limit values unit variable clock freq. = 2 mhz to 12 mhz min. max. oscillator period clp 83.3 500 ns high time tcl h 20 clp-tcl l ns low time tcl l 20 clp-tcl h ns rise time t r C12ns fall time t f C12ns oscillator duty cycle dc 0.5 0.5 C
semiconductor group 5-9 device specifications c505a 5.5 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle) v cc = 5v +10%, -15%; v ss =0v t a =0 to 70 c for the sab-c505a versions t a = -40 to 85 c for the saf-c505a versions ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c505a to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 16-mhz clock duty cycle 0.4 to 0.6 variable clock 1/clp= 2 mhz to 16 mhz min. max. min. max. ale pulse width t lhll 48 C clp - 15 C ns address setup to ale t avll 10 C tcl hmin -15 C ns address hold after ale t llax 10 C tcl hmin -15 C ns ale to valid instruction in t lliv C 75 C 2 clp - 50 ns ale to psen t llpl 10 C tcl lmin -15 C ns psen pulse width t plph 73 C clp+ tcl hmin -15 Cns psen to valid instruction in t pliv C38C clp+ tcl hmin - 50 ns input instruction hold after psen t pxix 0C0 C ns input instruction float after psen t pxiz *) C15C tcl lmin -10 ns address valid after psen t pxav *) 20 C tcl lmin - 5 C ns address to valid instruction in t aviv C 95 C 2 clp + tcl hmin -55 ns address float to psen t azpl -5 C -5 C ns
device specifications c505a semiconductor group 5-10 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle, contd) external data memory characteristics parameter symbol limit values unit 16-mhz clock duty cycle 0.4 to 0.6 variable clock 1/clp= 2 mhz to 16 mhz min. max. min. max. rd pulse width t rlrh 158 C 3 clp - 30 C ns wr pulse width t wlwh 158 C 3 clp - 30 C ns address hold after ale t llax2 48 C clp - 15 C ns rd to valid data in t rldv C 100 C 2 clp+ tcl hmin - 50 ns data hold after rd t rhdx 0C0 C ns data float after rd t rhdz C 51 C clp - 12 ns ale to valid data in t lldv C 200 C 4 clp - 50 ns address to valid data in t avdv C 200 C 4 clp + tcl hmin -75 ns ale to wr or rd t llwl 73 103 clp + tcl lmin - 15 clp+ tcl lmin + 15 ns address valid to wr t avwl 95 C 2 clp - 30 C ns wr or rd high to ale high t whlh 10 40 tcl hmin - 15 tcl hmin + 15 ns data valid to wr transition t qvwx 5Ctcl lmin - 20 C ns data setup before wr t qvwh 163 C 3 clp + tcl lmin - 50 Cns data hold after wr t whqx 5Ctcl hmin - 20 C ns address float after rd t rlaz C0C 0 ns
semiconductor group 5-11 device specifications c505a ac characteristics (16 mhz, 0.4 to 0.6 duty cycle, contd) note: the 16 mhz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. external clock drive characteristics parameter symbol cpu clock = 16 mhz duty cycle 0.4 to 0.6 variable cpu clock 1/clp = 2 to 16 mhz unit min. max. min. max. oscillator period clp 62.5 62.5 62.5 500 ns high time tcl h 25 C 25 clp - tcl l ns low time tcl l 25 C 25 clp - tcl h ns rise time t r C 10 C 10 ns fall time t f C 10 C 10 ns oscillator duty cycle dc 0.4 0.6 25 / clp 1 - 25 / clp C clock cycle tcl 25 37.5 clp * dc min clp * dc max ns
device specifications c505a semiconductor group 5-12 5.6 ac characteristics (20 mhz, 0.5 duty cycle) v cc = 5v +10%, -15%; v ss =0v t a =0 to 70 c for the sab-c505a versions t a = -40 to 85 c for the saf-c505a versions ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c505a to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 20 mhz clock 0.5 duty cycle variable clock 1/clp = 2 mhz to 20 mhz min. max. min. max. ale pulse width t lhll 35 C clp - 15 C ns address setup to ale t avll 10 C clp/2 - 15 C ns address hold after ale t llax 10 C clp/2 - 15 C ns ale to valid instruction in t lliv C 55 C 2 clp - 45 ns ale to psen t llpl 10 C clp/2 - 15 C ns psen pulse width t plph 60 C 3/2 clp - 15 Cns psen to valid instruction in t pliv C 25 C 3/2 clp - 50 ns input instruction hold after psen t pxix 0C0 C ns input instruction float after psen t pxiz *) C 20 C clp/2 - 5 ns address valid after psen t pxav *) 20 C clp/2 - 5 C ns address to valid instruction in t aviv C 65 C 5/2 clp - 60 ns address float to psen t azpl - 5 C - 5 C ns
semiconductor group 5-13 device specifications c505a ac characteristics (20 mhz, 0.5 duty cycle, contd) external data memory characteristics parameter symbol limit values unit 20 mhz clock 0.5 duty cycle variable clock 1/clp = 2 mhz to 20 mhz min. max. min. max. rd pulse width t rlrh 120 C 3 clp - 30 C ns wr pulse width t wlwh 120 C 3 clp - 30 C ns address hold after ale t llax2 35 C clp - 15 C ns rd to valid data in t rldv C 75 C 5/2 clp- 50 ns data hold after rd t rhdx 0C0Cns data float after rd t rhdz C38C clp - 12ns ale to valid data in t lldv C 150 C 4 clp - 50 ns address to valid data in t avdv C 150 C 9/2 clp - 75 ns ale to wr or rd t llwl 60 90 3/2 clp - 15 3/2 clp + 15 ns address valid to wr t avwl 70 C 2 clp - 30 C ns wr or rd high to ale high t whlh 10 40 clp/2 - 15 clp/2 + 15 ns data valid to wr transition t qvwx 5Cclp/2 - 20C ns data setup before wr t qvwh 125 C 7/2 clp - 50 C ns data hold after wr t whqx 5Cclp/2 - 20C ns address float after rd t rlaz C0C0ns external clock drive characteristics parameter symbol limit values unit variable clock freq. = 2 mhz to 20 mhz min. max. oscillator period clp 50 500 ns high time tcl h 15 clp-tcl l ns low time tcl l 15 clp-tcl h ns rise time t r C10ns fall time t f C10ns oscillator duty cycle dc 0.5 0.5 C
device specifications c505a semiconductor group 5-14 program memory read cycle
semiconductor group 5-15 device specifications c505a data memory read cycle
device specifications c505a semiconductor group 5-16 data memory write cycle external clock drive on xtal1 tcl h tcl l clp t r t f 0.2 v cc 0.7 cc v - 0.1 mct03310
semiconductor group 5-17 device specifications c505a 5.7 otp memory characteristics 5.7.1 programming mode timing characteristics v cc = 5 v 10 %; v pp = 11.5 v 5%; t a = 25 c 10 c parameter symbol limit values unit min. max. pale pulse width t paw 35 C ns pmsel setup to pale rising edge t pms 10 C address setup to pale, prog , or prd falling edge t pas 10 C ns address hold after pale, prog , or prd falling edge t pah 10 C ns address, data setup to prog or prd t pcs 100 C ns address, data hold after prog or prd t pch 0Cns pmsel setup to prog or prd t pms 10 C ns pmsel hold after prog or prd t pmh 10 C ns prog pulse width t pww 100 C m s prd pulse width t prw 100 C ns address to valid data out t pad C75ns prd to valid data out t prd C20ns data hold after prd t pdh 0Cns data float after prd t pdf C20ns prog high between two consecutive prog low pulses t pwh1 1C m s prd high between two consecutive prd low pulses t pwh2 100 ns xtal clock period t clkp 83.3 500 ns
device specifications c505a semiconductor group 5-18 programming code byte - write cycle timing t paw t pas pale port 2 a0-7 port 0 pmsel1,0 d0-7 prog t pah t pcs a8-14 t pch t pwh t pww notes : prd must be high during a programming write cycle t pms h, h
semiconductor group 5-19 device specifications c505a verify code byte - read cycle timing t pas port 0 d0-7 prd t pah t pcs t prw notes : prog must be high during a programming read cycle t pch t pdh t prd t pdf pale pmsel1,0 t pms t paw port 2 a0-7 a8-14 h, h t pad t pwh
device specifications c505a semiconductor group 5-20 lock bit access timing version registers - read timing prd note : pale should be low during a lock bit read/write cycle pmsel1,0 h, l port 0 d0, d1 d0, d1 h, l prog t pcs t pms t pww t pmh t pch t pms t prd t prw t pmh t pdh t pdf d0-7 l, h e.g. fd h note : prog must be high during a programming read cycle t pms t prd t prw t pcs t pmh t pdh t pdf t pch prd pmsel1,0 port 2 port 0
semiconductor group 5-21 device specifications c505a 5.7.2 otp verification mode characteristics otp verification mode note: this mode cannot be entered into if otp protection levels of 1 to 3 are programmed. parameter symbol limit values unit min. typ max. ale pulse width t awd CclpCns ale period t acy C6 clpCns data valid after ale t dva CC2 clpns data stable after ale t dsa 4 clp C C ns p3.5 setup to ale low t as Ctcl h Cns oscillator frequency 1/ clp 4C6mhz
device specifications c505a semiconductor group 5-22 ac testing: input, output waveforms ac testing : float waveforms recommended oscillator circuits for crystal oscillator ac inputs during testing are driven at v cc - 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at v ihmin for a logic 1 and v ilmax for a logic 0. for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. xtal2 xtal1 external oscillator signal crystal mode : c = 20 pf 10 pf (incl. stray capacitance) crystal oscillator mode driving from external source xtal1 xtal2 n.c. c mhz 2 - 20 c
semiconductor group 5-23 device specifications c505a 5.8 package information p-mqfp-44-2 outline sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. smd = surface mounted device plastic package, p-mqfp-44-2 (smd) (plastic metric quad flat pack) g p m 0 5 6 2 2 dimensions in mm
semiconductor group 6-1 introduction c505a 6 index note: bold page numbers refer to the main definition part of sfrs or sfr bits. a a/d converter . . . . . . . . . . . . . . . .3-1C3-13 analog input pin selection . . . . . . . . 3-13 block diagram . . . . . . . . . . . . . . . . . . 3-2 calibration mechanisms . . . . . . . . . 3-12 clock selection . . . . . . . . . . . . . . . . . . 3-7 conversion time calculation . . . . . . . 3-10 conversion timing . . . . . . . . . . . . . . . 3-8 general operation . . . . . . . . . . . . . . . 3-1 registers . . . . . . . . . . . . . . . . . . .3-3C3-6 system clock relationship . . . . . . . . . 3-9 a/d converter characteristics . . . . .5-5C5-6 absolute maximum ratings . . . . . . . . . . 5-1 ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 ac characteristics . . . . . . . . . . . . .5-7C5-13 12 mhz timing . . . . . . . . . . . . . . .5-7C5-8 16 mhz timing . . . . . . . . . . . . . .5-9C5-11 20 mhz timing . . . . . . . . . . . . . 5-12C5-13 ac testing float waveforms . . . . . . . . . . . . . . . 5-22 input/output waveforms . . . . . . . . . . 5-22 acc . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9 adcl1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 adcl1-0 . . . . . . . . . . . . . . . . . . . . . . . . 3-5 adcon0 . . . . . . . . . . . . . 2-4, 2-5, 2-9, 3-4 adcon1 . . . . . . . . . . . . . . . . . 2-4, 2-9, 3-4 addath . . . . . . . . . . . . . . . . . 2-4, 2-9, 3-3 addatl . . . . . . . . . . . . . . . . . 2-4, 2-9, 3-3 adm . . . . . . . . . . . . . . . . . . . . . . . .2-9, 3-4 b b . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9 bd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 boff . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 brp . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 bsy . . . . . . . . . . . . . . . . . . . . . . . . .2-9, 3-4 btr0 . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 btr1 . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 c c/t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 cce . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 ccen . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-8 cch1 . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-8 cch2 . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-8 cch3 . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8 ccl1 . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8 ccl2 . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8 ccl3 . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8 clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 clkout . . . . . . . . . . . . . . . . . . . . . . . . .2-7 cmod . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cocah0 . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cocah1 . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cocah2 . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cocah3 . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cocal0 . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cocal1 . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cocal2 . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cocal3 . . . . . . . . . . . . . . . . . . . . . . . . .2-8 cpuupd . . . . . . . . . . . . . . . . . . . . . . . .2-10 cr . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 crch . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 crcl . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 cswo . . . . . . . . . . . . . . . . . . . . . . . 2-3, 2-8 cy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 d db0 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11 db1 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11 db2 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11 db3 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11 db4 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11 db5 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11 db6 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11 db7 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11 dc characteristics . . . . . . . . . . . . . . 5-2C5-3 device characteristics . . . . . . . . . 5-1C5-23 dir . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 dlc . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 dph . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-7 dpl . . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-7 dpsel . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-7 e ea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 eadc . . . . . . . . . . . . . . . . . . . . . . . 2-8, 3-6 eale . . . . . . . . . . . . . . . . . . . . . . . . 1-8, 2-8 ean0 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 ean1 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 ean2 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 ean3 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 ean4 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 ean5 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
semiconductor group 6-2 introduction c505a ean6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ean7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ean7-0 . . . . . . . . . . . . . . . . . . . . . . . . 3-13 ecan . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 eie . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 et0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 et1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 et2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ewpd . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ewrn . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 ex0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ex1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ex3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 ex4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 ex5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 ex6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 exen2 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 exf2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 f f0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 f1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 features . . . . . . . . . . . . . . . . . . . . . . . . 1-2 functional units . . . . . . . . . . . . . . . . . . . 1-1 g gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 gf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 gf1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 gms0 . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 gms1 . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 i i3fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 iadc . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 id12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 id17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 id20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 id28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 id4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 idls . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 ie0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ie1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ien0 . . . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-7 ien1 . . . . . . . . . . . . . . . . 2-4, 2-5, 2-8, 3-6 iex3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 iex4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 iex5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 iex6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 init . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 int4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 int5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 intid . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 intpnd . . . . . . . . . . . . . . . . . . . . . . . .2-10 ip0 . . . . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-7 ip1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-8 ir . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 ircon . . . . . . . . . . . . . . . . . . 2-4, 2-8, 3-6 it0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 it1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 l lar0 . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 lar1 . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 lec0 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 lec1 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 lec2 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 lgml0 . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 lgml1 . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 lmlm0 . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 lmlm1 . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 logic symbol . . . . . . . . . . . . . . . . . . . . . .1-3 m m0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 m1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 mcfg . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 mcr0 . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 mcr1 . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 memory organization . . . . . . . . . . . . . . .2-1 data memory . . . . . . . . . . . . . . . . . . . .2-2 general purpose registers . . . . . . . . . .2-2 memory map . . . . . . . . . . . . . . . . . . . .2-1 program memory . . . . . . . . . . . . . . . .2-2 msglst . . . . . . . . . . . . . . . . . . . . . . . .2-10 msgval . . . . . . . . . . . . . . . . . . . . . . . .2-10 mx0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 mx1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 mx2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 mx2-0 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4 n newdat . . . . . . . . . . . . . . . . . . . . . . .2-10
semiconductor group 6-3 introduction c505a o otp memory . . . . . . . . . . . . . . . . .4-1C4-13 basic mode selection . . . . . . . . . . . . 4-5 pin configuration . . . . . . . . . . . . . . . . 4-1 program/read operation . . . . . . . . . . . 4-7 otp protection protected verification mode . . . . . . . 4-12 verification example . . . . . . . . . . . . 4-13 verification timing . . . . . . . . . . . . . . 4-12 ov . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 owds . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 p p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 p0 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-7 p1 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-7 p1ana . . . . . . . . . . . . . . . . . . 2-4, 2-7, 3-13 p2 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-7 p3 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-8 p4 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9 package information . . . . . . . . . . . . . . 5-23 pcon . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7 pcon1 . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7 pde . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 pds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 pin configuration . . . . . . . . . . . . . . . . . . 1-4 pin definitions and functions (normal mode) 1-5C1-9 pin definitions and functions (otp mode) 4-3C4-4 psw . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-8 r rb8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 rd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 recommended oscillator circuits . . . . . 5-22 ren . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 rmap . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 rmtpnd . . . . . . . . . . . . . . . . . . . . . . . 2-10 rs0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 rs1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 rxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 rxdc . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 rxie . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 rxok . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 s sbuf . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7 scon . . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-7 sd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 sie . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 sjw . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 sm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 sm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 sm2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 smod . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 sp . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-7 special function registers . . . . . . . . . . .2-3 access with rmap . . . . . . . . . . . . . . .2-3 can registers - address ordered 2-10C2-11 table - address ordered . . . . . . . 2-7C2-9 table - functional order . . . . . . . . 2-4C2-6 sr . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10 srelh . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8 srell . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-7 swdt . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 swi . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 syscon . . . . . . . . . . . . . . . . . 2-3, 2-4, 2-8 t t0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 t2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 t2cm . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 t2con . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-8 t2ex . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 t2i0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 t2i1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 t2ps . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 t2r0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 t2r1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 tb8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 tcon . . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-7 test . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 tf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 tf1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 tf2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 th0 . . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-7 th1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-7 th2 . . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8 ti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 timings data memory read cycle . . . . . . . . . .5-15 data memory write cycle . . . . . . . . . .5-16 external clock timing . . . . . . . . . . . . .5-16
semiconductor group 6-4 introduction c505a otp verification mode . . . . . . . . . . . 5-21 program memory read cycle . . . . . . 5-14 tl0 . . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7 tl1 . . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7 tl2 . . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-8 tmod . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7 tr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 tr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 tseg1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 tseg2 . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 txd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 txdc . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 txie . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 txok . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 txrq . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 u uar0 . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 uar1 . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 ugml0 . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 ugml1 . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 umlm0 . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 umlm1 . . . . . . . . . . . . . . . . . . . . .2-6, 2-10 v vr0 . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9 vr1 . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9 vr2 . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9 w wdt . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 wdtpsel . . . . . . . . . . . . . . . . . . . . . . . 2-7 wdtrel . . . . . . . . . . . . . . . . . . . . .2-5, 2-7 wdts . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 x xmap0 . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 xmap1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 xpage . . . . . . . . . . . . . . . . . . . . . .2-4, 2-7 xtd . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

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